A pipelined semi-parallel LDPC Decoder architecture for DVB-S2
نویسندگان
چکیده
The implementation of an LDPC Decoder for the DVB-S2 standard is a challenging task, specially because of 1) the large parity-check matrices and 2) the iterative decoding algorithm, which may represent a bottleneck within the receiver data flow. This paper presents a pipelined architecture for LDPC decoding based on a semi-parallel implementation of the Minimum-Sum algorithm, a simplification of the BeliefPropagation decoding algorithm, and the results of a model simulation and an early synthesis for FPGA prototyping.
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